Semiconductor Design Engineer – Digital Library & Timing Specialist

About the role

Teradyne’s Semiconductor Test Division in Costa Rica is looking for a Semiconductor Design Engineer to ensure the robustness and efficiency of custom digital libraries and verify timing constraints using Cadence tools. You will play a key part in delivering high‑quality chip designs that meet performance and reliability targets.

Key responsibilities

• Develop detailed circuit specifications for mixed‑signal circuits and design transistor‑level topologies.
• Provide layout guidance for high‑speed circuits and optimize designs through Cadence simulations across process corners.
• Collaborate with library development teams to create and enhance digital standard‑cell libraries.
• Characterize timing constraints (setup, hold, corner cases) using Liberate and optimize library elements.
• Perform static timing analysis (STA) with Cadence Innovus, Tempus, Encounter and Liberate.
• Debug and resolve timing violations, ensuring compliance with design specifications.
• Work closely with physical design teams for library integration and compatibility.
• Maintain library documentation, timing models, and contribute to quality‑assurance activities.

Required profile

• Strong passion for precision and high‑quality semiconductor design.
• Experience in digital library development and timing analysis.
• Ability to work collaboratively with cross‑functional engineering teams.

Required skills

• Cadence EDA tools (simulation, STA, Innovus, Tempus, Encounter, Liberate).
• Mixed‑signal circuit design and transistor‑level topology creation.
• Digital standard‑cell library development and characterization.
• Static timing analysis and timing‑violation debugging.

What we offer

• Opportunity to work on cutting‑edge semiconductor test technology.
• Inclusive and diverse work environment.
• Professional growth within a global technology leader.