CPLD/FPGA DV Engineer

About the role

The CPLD/FPGA Design Verification Engineer will join HPE’s VLSI engineering team, working on cutting‑edge server and computer architecture components. This hybrid position expects the candidate to be onsite two days per week, collaborating with both internal and outsourced partners to deliver high‑quality VLSI prototypes and production solutions.

Key responsibilities

• Design and simulate portions of server architecture and algorithms following VLSI engineering principles.
• Develop, verify, and test CPLD/FPGA and other VLSI circuits using industry‑standard simulation tools.
• Collaborate with management to report design status, project progress, and resolve technical issues.
• Participate in cross‑functional project teams to ensure designs meet quality, schedule, and cost targets.
• Support prototype fabrication and evaluate experimental results to guide production readiness.

Required profile

• Bachelor’s degree in Electrical, Electronic, Computer Engineering or a related field.
• 0–2 years of experience in VLSI design, verification, or implementation.
• Strong analytical and problem‑solving abilities.
• Understanding of digital logic, computer architecture, and VLSI principles.

Required skills

• VLSI design
• Design verification
• Digital logic
• Computer architecture
• CPLD
• FPGA