Experienced IP Logic Design Engineer

About the role

The Foundational Security team (FST) at Intel is seeking an experienced digital logic designer to develop and validate scalable IP for hardware security across multiple market segments. You will work closely with verification engineers, RTL designers, micro‑architects, and SoC teams to deliver high‑quality IP blocks.

Key responsibilities

• Develop RTL code, simulation models, and logic designs for IP blocks, cell libraries, and functional units.
• Participate in defining architecture and micro‑architecture features of the assigned IP.
• Optimize RTL for power, performance, area, timing, and physical implementation goals.
• Review verification plans, troubleshoot failing RTL tests, and ensure design correctness.
• Support SoC customers during integration and verification of the IP.
• Drive quality‑assurance compliance for smooth IP‑SoC handoff.

Required profile

• Strong analytical and debugging abilities.
• Creative problem‑solving mindset.
• Excellent communication, organization, and teamwork skills.
• Passion for hardware design or validation and a focus on quality and delivery.

Required skills

• RTL coding and logic design.
• Simulation and verification methodologies.
• Experience with IP development and integration.

What we offer

• Opportunity to contribute to Intel’s hardware security roadmap.
• Collaboration with cross‑functional engineering teams.
• Professional growth in a leading semiconductor environment.