Verification Engineer – FPGA Verification

About the role

Teradyne’s Nextest FPGA team is seeking an experienced Verification Engineer to lead functional verification of complex FPGA designs. You will work closely with design, software and hardware teams to ensure product quality and on‑time delivery.

Key responsibilities

• Develop and execute verification plans and strategies for FPGA projects.
• Create SystemVerilog/UVM testbenches, verification components and self‑checking environments.
• Implement data checkers, assertions and coverage models to achieve 100 % functional and code coverage.
• Debug failures using waveforms, log analysis and cross‑team collaboration.
• Integrate verification IP and support protocol verification (PCIe, AXI).

Required profile

• Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering or related field.
• Minimum 8 years of hands‑on digital design functional verification experience.
• Strong English communication skills.

Required skills

• SystemVerilog and UVM methodology.
• Experience with industry protocols such as PCIe and AXI.
• Proficiency with Cadence Xcelium and SimVision EDA tools.
• Ability to build testbenches, verification components and integrate verification IP.