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ASIC Verification Engineer (Mid-Level and Senior)

Cornelis Networks

New
Mid 🇬🇧 English
UVM Formal verification TCL Python Perl

Job description

About the role

Cornelis Networks builds high-performance scale-out networking solutions for AI and HPC datacenters, integrating hardware, software and system-level technologies for GPU, CPU and accelerator clusters. It is hiring mid-level and senior ASIC verification engineers to verify SoCs used in high-performance computing, data analytics and AI interconnect solutions. The role may be performed remotely from Costa Rica via an Employer of Record.

Key responsibilities

  • Take part in developing UVM environments to verify RTL at block, unit and SoC levels
  • Write and run tests according to verification plans
  • Instrument test benches for functional and code coverage, and collect and analyze coverage results
  • Run formal verification of block-level RTL
  • Take part in post-silicon verification

Required profile

  • Bachelor's degree in Computer Engineering, Computer Science or Electrical Engineering
  • 3+ years of post-college experience in verification
  • 3+ years of post-college experience in one or more scripting languages (TCL, Python, Perl, shell scripting)
  • 3+ years of post-college experience validating complex SoCs with multiple clock and reset domains
  • Ability to read, write and speak English at professional working level

Required skills

  • UVM-based testbench development
  • Formal verification of RTL
  • Scripting in TCL, Python, Perl or shell

Preferred qualifications

  • M.S. degree in Computer Engineering, Computer Science or Electrical Engineering
  • Track record of first-pass success in ASIC and systems

The company offers a competitive package including base salary, performance incentives and equity participation, with possible additional benefits depending on location.

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Published 3 hours ago

Expires 1 month from now

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Cornelis Networks