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ASIC Design Engineer

Cornelis Networks

New Remote
Remote Senior 🇬🇧 English
Verilog RTL Timing closure Physical design Ethernet protocols

Job description

About the role

Cornelis Networks builds high-performance scale-out networking solutions for AI and HPC datacenters, integrating hardware, software and system-level technologies. It is hiring ASIC Design Engineers with deep experience in the key areas needed to build SoCs for high-performance computing, data analytics and AI interconnect solutions. The role may be performed remotely from Costa Rica via an Employer of Record.

Key responsibilities

  • Implement advanced Ethernet protocols for next-generation Ethernet ASICs.
  • Write microarchitecture specifications.
  • Pre-silicon: define timing constraints for the RTL block and work with Physical Design engineers on timing optimization.
  • Pre-silicon: work with verification engineers to create block and system-level test plans and ensure adequate coverage.
  • Post-silicon: work with hardware, firmware and software engineers to resolve ASIC issues.

Required profile

  • B.S. or M.S. degree in Computer or Electrical Engineering.
  • 3+ years of post-college experience in digital design.
  • Relevant experience in timing closure and familiarity with modern physical design methodologies.
  • Demonstrated strength in system-level debugging and root cause analysis.
  • Strong verbal and written communication skills.

Required skills

  • Proficiency in Verilog and SystemVerilog.
  • Preferred: experience with Ethernet architecture and networking protocols, including Ethernet adapter and switch protocols.
  • Preferred: experience with multiple clock designs and asynchronous interfaces.

What we offer

  • Base salary, performance incentives and equity participation.
  • Paid holidays and flexible work arrangements depending on location.

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Published 2 days ago

Expires 1 month from now

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Cornelis Networks