RTL Design Engineer – Mixed Signal ASICs

About the role

Teradyne is seeking an experienced RTL Design Engineer to join its Silicon Technology Engineering Digital ASIC Group in Costa Rica. You will work on next‑generation mixed‑signal ASICs that power Teradyne’s test and automation solutions, collaborating closely with analog designers and product architects.

Key responsibilities

• Develop specifications, micro‑architecture, and RTL for mission‑critical blocks.
• Integrate industry‑standard and custom IPs into the design.
• Partner with verification teams to create test plans, debug issues, and achieve coverage closure.
• Provide timing constraints and support static timing analysis for physical design.
• Assist with post‑silicon bring‑up, lab debugging, and mentor junior designers.

Required profile

• BSEE or MSEE in Electrical Engineering or a related field.
• Minimum 5 years of professional experience in digital logic design.
• Proven ability to work across all development phases from specification to silicon bring‑up.

Required skills

• Verilog RTL coding.
• Micro‑architecture development.
• IP integration (standard and custom).
• Verification methodology and test‑plan creation.
• Static timing analysis and timing closure.
• Physical design support.
• Silicon bring‑up and debug.