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Power Integrity Intern - Physical Design Engineering

Intel · San Jose

Nouveau
Prácticas Hybrid Junior 🇬🇧 English
Sigrity PowerSI SiWave Hspice Matlab Ansys HFSS PCB design JMP

Description du poste

About the role

Intel is looking for a Physical Design Engineering Undergraduate Intern in its Silicon and Platform Engineering Group (SPE) in San Jose, Costa Rica. The intern contributes to the physical implementation of silicon and platform designs so they are ready for manufacturing, gaining hands-on experience in design flows, power integrity analysis and validation of high-speed interconnects. The role is open to students pursuing a Bachelor's or Master's degree in Electronics or Electrical Engineering.

Key responsibilities

  • Assist in the physical implementation of package and platform designs, contributing to power integrity and high-speed interconnect validation.
  • Collaborate with cross-functional teams to support design scalability, automation and manufacturability.
  • Take part in verification and signoff processes to ensure compliance with performance and manufacturing standards.
  • Apply theoretical knowledge to practical projects, including power integrity analysis and physical design optimization.
  • Support design initiatives using advanced tools and methodologies.

Required profile

  • Pursuing a Bachelor's degree in Electronics or Electrical Engineering with at least 50% of coursework completed, or a Master's degree in the same field; Bachelor's candidates need 0-1 years of hands-on experience, Master's candidates need none.
  • Proficiency in written and spoken English.
  • At least 1-2 courses in electrical or electromagnetic fundamentals.
  • Minimum 80% GPA.
  • Availability to work at least 22.5 hours per week during the internship and commitment to stay at least 1 year.
  • Legal authorization to work in Costa Rica.

Required skills

  • Preferred: familiarity with electrical simulation tools such as Sigrity PowerSI, SiWave, Hspice, Matlab or Ansys HFSS.
  • Preferred: experience with PCB design or circuit simulators.
  • Preferred: knowledge of statistical analysis tools such as JMP or equivalent.

The posting states eligibility for a hybrid work model, though details are subject to change. No recruitment fees are charged.

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Le contrat proposé est un Prácticas basé à San Jose.

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Intel

San Jose