PnP Lab Engineer Intern (Physical Design)

About the role

Intel's Silicon and Platform Engineering Group (SPE) is looking for a Physical Design Engineering undergraduate intern in San Jose, Costa Rica. The intern contributes to the physical implementation of silicon designs so they are ready for manufacturing, working with cross-functional teams on design scalability and manufacturability. The internship requires an on-site presence and at least 22.5 hours per week.

Key responsibilities

• Measure, test and analyze key performance and power indicators for architecture enhancements and optimizations.
• Perform power measurements and analysis across subsystems and domains using power measurement tools and logic analyzers.
• Analyze new proof-of-concept systems and technology readiness for system-level performance and responsiveness using performance monitoring tools.
• Change configurations for testing and measurement with SOC, platform components and display panels, install device drivers and firmware, and run benchmark workloads.
• Understand how power, performance and responsiveness indicators affect client product architectures such as CPU, GPU, NPU and I/O.
• Write test scripts for data execution and tasks improvement to enable system-level measurements and analysis.
• Adapt AI to daily tasks.

Required profile

• Bachelor's degree in Electronics or Electrical Engineering with at least 50% of courses completed, or a Master's degree in the same field; Bachelor's candidates need 0-1 years of hands-on experience, Master's candidates need none.
• Proficiency in written and spoken English.
• At least 1-2 courses in electrical/electromagnetic fundamentals and a minimum 80% GPA.
• Availability for at least 22.5 hours per week during the internship and willingness to stay at least 1 year.
• Legal authorization to work in Costa Rica.

Required skills

• Preferred: Python, C++ and batch programming skills.
• Preferred: experience debugging complex signal integrity challenges and working with interdisciplinary teams.