Senior Analog Layout Engineer – Semiconductor Design

About the role

We are seeking a Senior Analog Layout Engineer to lead the physical design of complex analog and mixed‑signal ASIC blocks for Teradyne’s next‑generation test and automation platforms. The role involves creating manufacturable layouts in advanced FinFET processes and collaborating closely with circuit designers and physical design teams.

Key responsibilities

• Lead layout design and integration of analog and mixed‑signal ASIC blocks using Cadence Virtuoso.
• Develop floorplans, placement, routing, and top‑level integration strategies for FinFET and other advanced‑node technologies.
• Partner with circuit designers to optimise performance, power, area and reliability.
• Apply layout techniques for device matching, symmetry, shielding, substrate isolation and noise control.
• Perform and sign‑off DRC, LVS, ERC and parasitic extraction to ensure first‑pass silicon success.
• Support high‑speed precision circuits such as ADCs, DACs, PLLs, reference generators and SerDes‑adjacent blocks.
• Provide technical leadership through layout reviews, methodology development and best‑practice implementation.
• Collaborate on timing closure, power integrity and signal integrity goals and contribute to tape‑out, foundry interaction and post‑silicon debug.
• Document layout flows, checklists and design guidelines; mentor junior engineers.

Required profile

• BS degree in Electronic, Electrical or Computer Engineering or equivalent industry experience.
• 10+ years of hands‑on analog or mixed‑signal IC layout experience.
• Proven expertise with advanced FinFET or deep‑submicron analog processes.
• Strong track record of delivering high‑performance, reliable ASICs on schedule.

Required skills

• Cadence Virtuoso
• DRC, LVS, ERC, parasitic extraction
• FinFET technology
• Analog and mixed‑signal ASIC layout
• ADC, DAC, PLL, reference and SerDes‑adjacent circuit layout
• Floorplanning, placement and routing
• Timing closure, power integrity and signal integrity analysis
• Tape‑out, foundry interaction and post‑silicon debug