Senior Physical Design Engineer

About the role

Intel's Central Engineering Group (CEG) is seeking a Senior Physical Design Engineer to drive the implementation of custom IP and SoC designs from RTL through to GDS. You will work on cutting‑edge silicon for IoT, AI, Edge and networking applications, helping Intel maintain its market leadership.

Key responsibilities

• Perform full physical design flow: synthesis, place & route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and noise analysis.
• Run verification and sign‑off flows, including formal equivalence, power integrity, layout verification, electrical rule checking, and structural design reviews.
• Analyze results, recommend architectural improvements, and optimize designs for power, frequency, and area.
• Contribute to methodology development and flow automation for physical design.
• Provide expertise to cross‑functional teams on clock design, timing closure, multi‑power‑domain analysis, and DFT.

Required profile

• Bachelor’s or Master’s degree in Electronic, Electrical or Computer Engineering (or equivalent).
• Minimum 3 years of experience with synthesis, place & route tools and sign‑off flows.
• At least 3 years of Unix/Linux and shell programming experience.
• Advanced English proficiency and ability to communicate with cross‑site partners.
• Costa Rican unrestricted work permit.

Required skills

• RTL to GDS physical design implementation.
• Synthesis, place & route, clock tree synthesis, floor planning.
• Static timing analysis, power distribution, reliability and noise analysis.
• Formal equivalence verification, power integrity analysis, layout verification, electrical rule checking.
• Design for test (DFT) and multi‑power‑domain analysis.
• Unix/Linux operating systems and shell scripting.

What we offer

• Opportunity to work on industry‑leading silicon projects.
• Collaboration with a dynamic, cross‑functional engineering team.
• Competitive compensation and benefits package.