ASIC Design Engineer

About the role

We are looking for an ASIC Design Engineer to develop next‑generation Ethernet ASICs that power AI and HPC networking solutions. The role involves working on micro‑architecture, pre‑silicon timing, verification and post‑silicon debugging in a fast‑growing, globally distributed team.

Key responsibilities

• Implement advanced Ethernet protocols for next‑generation ASICs.
• Write micro‑architecture specifications and define RTL block timing constraints.
• Collaborate with physical design engineers to achieve timing closure.
• Partner with verification engineers to create test plans and ensure design coverage.
• Work with hardware, firmware and software teams to resolve post‑silicon ASIC issues.

Required profile

• B.S. or M.S. in Computer or Electrical Engineering.
• 3+ years of digital design experience with Verilog and SystemVerilog.
• Experience in timing closure and modern physical design methodologies.
• Strong system‑level debugging and root‑cause analysis skills.
• Excellent verbal and written communication abilities.

Required skills

• Verilog
• SystemVerilog
• Digital design and RTL development
• Timing closure
• Physical design methodologies
• Ethernet protocol architecture
• Multiple clock and asynchronous interface design
• System‑level debug

What we offer

• Competitive compensation package.
• Remote work from Costa Rica via an Employer of Record.
• Opportunity to work on cutting‑edge AI and HPC networking technologies.