Power Integrity Engineer
Intel · San Jose
Description du poste
About the role
Intel's Client Computing and Physical AI Group is seeking a Power Integrity Engineer to design and verify power delivery networks for client, edge, and physical AI platforms. The role focuses on ensuring optimal power delivery across silicon, packages, and boards to support high‑performance computing solutions.
Key responsibilities
- Architect and implement power integrity solutions, including voltage rail merging, isolation schemes, and decoupling strategies.
- Develop and simulate electrical models from DC to high‑frequency domains for power delivery networks.
- Define design constraints and guide package and board component implementation for optimal performance.
- Perform power noise analysis and measurements, correlating results with pre‑silicon estimations.
- Collaborate with silicon integration, package design, and die floor planning teams to optimize decoupling partitions and voltage regulation.
- Develop platform‑level specifications and validation methods to continuously improve power integrity methodologies.
Required profile
- Bachelor's degree in Electrical or Electronic Engineering.
- Minimum 3 years of hands‑on experience in electrical design engineering at silicon, package, or board level.
- Unrestricted permanent right to work in Costa Rica.
- Strong written and oral communication skills in English.
Required skills
- Proficiency with electrical simulation tools such as Sigrity PowerSI, PowerDC, HSpice, and Matlab.
- Experience using package and board CAD tools like Cadence Allegro or Mentor Graphics.
- Knowledge of power noise analysis, decoupling strategies, and voltage regulation schemes.
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Intel
San Jose